Recently, a structure in which a functional element having a particular function is disposed on the top of a semiconductor substrate has been used to enhance integration of a semiconductor integrated circuit. However, the disadvantage of using this structure is that characteristics of the functional element deteriorate if a foundation of the functional element is not planarized.
A magnetic random access memory is described as one such example.
In the magnetic random access memory, for example, one memory cell comprises a switching element (e.g., a field-effect transistor [FET]) disposed on a surface region of a semiconductor substrate, and a magnetoresistive element disposed on the top of the switching element.
The basic structure of the magnetoresistive element is a stack structure comprising a magnetic free layer having a variable magnetization, a magnetic pinned layer having an invariable magnetization, and a tunnel barrier layer disposed therebetween.
In such a magnetic random access memory, uniform thickness of the tunnel barrier layer and uniform quality of a material constituting this layer are indispensable to the improvement of the magnetic property of the magnetoresistive element. However, since the tunnel barrier layer is extremely thin (10 nm or less), the formation state of this extremely thin film deteriorates and the thickness of the tunnel barrier layer and the quality of the material constituting this layer cannot be uniform if the foundation of the tunnel barrier layer is not planar. As a result, the magnetic property of the magnetoresistive element cannot be improved.
To address such a problem, there has been suggested a technique for polishing a ferromagnetic (magnetic pinned) or antiferromagnetic layer serving as the foundation of the tunnel barrier layer so that its maximum roughness may be 0.5 nm or less.
However, according to this technique, a surface of the ferromagnetic or antiferromagnetic layer is directly polished. Thus, the ferromagnetic or antiferromagnetic layer is damaged by stress during the polishing, and the magnetic property of the magnetoresistive element deteriorates. Moreover, the ferromagnetic or antiferromagnetic layer varies in thickness, which leads to the variation of the magnetic property of the magnetoresistive element.
Furthermore, according to this technique, the magnetoresistive element (magnetic free layer/tunnel barrier layer/magnetic pinned layer) is not disposed immediately on a contact plug. The reason is that a magnetic field is used to write into the magnetoresistive element, so that if the magnetoresistive element is disposed immediately on the contact plug, it is difficult to apply the magnetic field to the magnetoresistive element.
Therefore, according to this technique, integration of the semiconductor integrated circuit cannot be enhanced by the size reduction of the memory cell.